The present invention relates to a semiconductor memory device; and, more specifically, the invention relates to a memory cell array system capable of accessing (inputting and outputting) an ultra-large number of bits in a dynamic memory simultaneously.
In connection with various semiconductor memory devices that have been studied by the inventor of this invention, such as DRAMs, there have been growing demands on the memory chip for an increased number of bits to increase the effective band width (frequencyxc3x97number of input/output bits) of the semiconductor memory system. However, it is not easy to realize an input/output width having an ultra-large bit number, more than 32 bits, such as 128 bits, while preventing an increase in the area of the chip. To realize this requires an improvement in the memory cell array.
A technique for constructing I/O lines in a hierarchical structure is disclosed in Japanese Patent Laid-Open No. 178158/1998, Japanese Patent Laid-Open No. 288888/1997, U.S. Pat. No. 5,657,286 (that corresponds to Japanese Patent Laid-Open No. 334985/1995) and U.S. Pat. No. 5,546,349 (that corresponds to Japanese Patent Laid-Open No. 8251/1997).
Regarding semiconductor memory devices such as the DRAMs mentioned above, the configuration of the DRAM as a basis for the present invention and the problems, thereof as studied by the inventor will be explained with reference to FIGS. 17a to 20.
FIG. 17a represents an example of a non-hierarchical input/output line system, which is used in 16 Mb DRAMs and 64 Mb DRAMs. The input/output lines IO are arranged on sense amplifiers in parallel with word lines and directly connected to a main amplifier. When a column selection signal line YS is on, the bit lines (BLT, BLB) and the input/output lines IOT, IOB are connected via MOS switches in the sense amplifier. To reduce the parasitic capacitance of the input/output lines IOa, 64 Mb DRAM is formed in a 16 kWxc3x974 kBL pair configuration with the word lines set in the direction of the shorter side, as shown in FIG. 17b. In this system, when multiple bit memory cells are to be accessed (read/written) simultaneously, the number of input/output lines on the sense amplifiers increases (two for each set), which in turn increases the dimension of the sense amplifiers.
In the 64 Mb synchronous DRAM of FIG. 17b, the number of word lines that can be selected in one bank operation is limited to two by the refresh cycle (address pin) standard. If the input and output of 16 bits are performed in the sense amplifier alternate arrangement, it is necessary to arrange four IO pairs on one sense amplifier. If 32 bits are to be input and output, eight IO pairs need to be arranged on a single sense amplifier, increasing the dimension of the sense amplifiers. Because the IO lines are non-hierarchical, the junction capacitance and line capacitance of a large number of MOS switches become parasitic capacitance of the input/output lines IO, causing degradations in the reading and writing speeds.
FIG. 18a represents an example of a hierarchical input/output line system. The principle of the hierarchical input/output line system is disclosed in Japanese Patent Publication No. 59712/1992, and the principle of a technique for combining the hierarchical input/output line system and the hierarchical word line system is disclosed in Japanese Patent Laid-Open No. 181292/1996. The input/output lines comprise local input/output lines LIO and main input/output lines MIO. The local input/output lines LIO are arranged on the sense amplifiers and are associated with a small number of memory cell arrays. In cross areas, the local input/output lines LIO and the main input/output lines MIO are connected by switches MOS. In the case of this figure, the switches MOS between the lines LIO and MIO are analog gates of NMOS and PMOS type . By controlling these gates using sense amplifier precharge signals BLEQ, BLEQB, the switch MOS in the activated sense amplifier is turned on and the switch MOS in the deactivated sense amplifier is turned off. The main input/output lines MIO are arranged on subword drivers perpendicular to the local input/output lines LIO and straddle a number of memory cell arrays.
The hierarchical input/output line system has the following advantages. A first advantage is that it can reduce the total parasitic capacitance associated with the local input/output lines LIO and the main input/output lines MIO and thereby can speed up accesses. A second advantage is that, by dividing the local input/output lines LIO horizontally into a number of sections, it is easier to realize xc3x9716 bits and xc3x9732 bits more easily than it is by the non-hierarchical system shown in FIGS. 17a and 17b. For example, when one word line is selected in FIG. 18a, a number of main input/output line MIO pairs are picked up vertically along a column of subword drivers by the LIO-MIO switch in the cross area. It is, however, significantly harder to realize xc3x9764 bits or more. The reason for this is that, because the main input/output lines MIO are arranged on the subword drivers in parallel with the column selection signal lines YS, the number of bits is limited by the number of subword driver columns. If xc3x9764 bits or more are to be realized, the number of MOS switches in the cross area increases and the number of MIOs on the subword drivers also increases, making the layout more difficult.
FIGS. 19a and 19b represent circuits associated with a memory cell array, also showing subword driver areas 17 (word drivers in the hierarchical word line system) adjacent to a memory cell array area 15 and also a sense amplifier area 16. Sense amplifier drivers and LIO-MIO switches are arranged in cross areas where the sense amplifiers and the subword drivers cross each other (in the hierarchical word line system, cross areas where shared sense amplifiers (shared by upper and lower memory cell arrays) and word drivers cross each other). It is assumed that overdrive sense amplifiers using VDDCLP are used. In this way, a large number of circuits need to be arranged in narrow cross areas defined by the sense amplifiers and the subword drivers and the layout is significantly more difficult. The hierarchical input/output line system requires incorporating LIO-MIO switches, LIO half-precharge circuits and MIO distributed high-precharge circuits, thereby making layout very difficult. Further, increasing the number of bits to more that 64 bits increases the number of LIO-MIO switches. The number of main input/output line MIO pairs extending vertically increases as the number of bits increases and this is a limiting factor affecting the subword driver area.
FIG. 20 is an explanatory diagram showing how the parasitic capacitance is reduced in the hierarchical input/output line system. The hierarchical input/output lines aim to reduce the total parasitic capacitance of LIO and MIO by dividing the local input/output lines LIO and the main input/output lines MIO. The parasitic capacitance of the local input/output lines LIO is the sum of the line capacitance of a second metal line hierarchy M2 and the junction capacitance of m YS switches MOS in the sense amplifier when the lines cross one to four memory cell arrays. The parasitic capacitance of the main input/output lines MIO is the sum of the line capacitance of a third metal line hierarchy M3 and the junction capacitance of LIO-MIO switches MOS in the cross area when the lines cross 2n memory cell arrays. The LIO parasitic capacitance of deactivated memory cell array is not seen. Hence, the occasions where the hierarchical input/output line system is greatly effective in capacitance reduction are when the parasitic capacitance of the local input/output lines LIO is large (LIO are shared by a large number of memory cell arrays arranged in a horizontal direction) and when the value n is large. The junction capacitance of the LIO-MIO switches MOS in the cross area increases as the MOS dimension increases. When the reduction rate of the overall parasitic capacitance is small, the conduction resistance of the switches MOS renders the hierarchical input/output line system not so effective in increasing the access speed when compared with the non-hierarchical input/output line system.
An object of the invention therefore is to provide a semiconductor memory device which can increase the number of bits while considering the parasitic capacitance of the input/output lines, particularly by using an input/output line system wired over the memory cell arrays.
These and other objects and novel features of the invention will become apparent from the description of this specification and the accompanying drawings.
Representative aspects of the invention disclosed in this patent application may be briefly explained below.
The semiconductor memory device according to the invention is applied to an input/output line system that is suited for simultaneous access of a large number of bits. The device does not cause a layout burden in the cross areas nor increase the number of input/output lines on the subword drivers.
A first means for increasing the number of bits uses lines on memory cell arrays (either or both of a second metal line hierarchy M2 and a third metal line hierarchy M3).
A second means uses a simple non-hierarchical input/output line system that eliminates switches in cross areas between local input/output lines and main input/output lines. Unlike FIG. 17, however, both horizontal and vertical input/output lines are used. The connection between the horizontal and vertical input/output lines is made by through holes on the sense amplifiers.
In more concrete terms, a plurality of memory cell sub-arrays are arranged two-dimensionally. The horizontal input/output lines (M2) on the horizontally arranged sense amplifiers are connected, by through holes on the sense amplifiers, to the vertical input/output lines (M3) on a separate hierarchy which cross the horizontal lines at right angles. The vertical input/output lines are arranged over the memory cell arrays in parallel with the column selection signal line so that they cover a plurality of memory cell arrays. The vertical input/output lines are connected to the main amplifiers and write drivers outside the memory cell arrays to enable a large number of bits to be input and output to and from a number of horizontally arranged memory cell arrays at the same time (parallelly).
Alternatively, the vertical input/output lines are arranged on the memory cell arrays in parallel with the column selection signal line. The vertical input/output lines are interconnected by the through holes on the memory cell arrays to convert them into an orthogonal direction. These are arranged to straddle a plurality of memory cell arrays and are connected to the main amplifiers and write drivers outside the memory cell arrays, thereby enabling a large number of bits to be input and output to and from each of the many horizontally arranged memory cell arrays simultaneously.
Alternatively, a plurality of memory cell sub-arrays are arranged two-dimensionally. Horizontal local input/output lines (M2) on the horizontally arranged sense amplifiers are converted by MOS switches in cross areas into vertical main input/output lines (M3) running over subword drivers in a direction perpendicular to the horizontal local input/output lines. In the subword driver column the vertical main input/output lines are again converted by through holes into horizontal M2, which is then converted by through holes on the memory cell arrays into the vertical main input/output lines (M3). The vertical main input/output lines are arranged on the memory cell arrays in parallel with the column selection signal line so that they run through a plurality of memory cell arrays. The vertical main input/output lines are connected to the main amplifier and the write driver to enable a large number of bits to be input and output to and from each of the many horizontally arranged sub-arrays simultaneously.
The above semiconductor memory device employs only the first means or a hierarchical input/output line system, which utilizes lines on the memory cell arrays to increase the number of bits while still using the switches in the cross areas between the local input/output lines and the main input/output lines. Although this does not simplify the cross areas, the increase in the number of input/output lines does not result in an increase in the sub word driver area. This will be explained later to some extent in the description of the embodiment of the invention.
Further, by combining the second means, with the first means, a non-hierarchical input/output line system as well as the lines on the memory cell arrays are utilized to increase the number of bits. This, in combination with an increased bit number, will lead to simplified cross areas. This will be explained later in great detail in the description of the embodiment of the invention.
Further, the semiconductor device comprises:
a first memory array having a plurality of first memory cells;
a second memory array having a plurality of second memory cells;
a first data line extending in a first direction and provided for the first memory array;
a second data line extending in the first direction and provided for the second memory array; and
a third data line extending in a second direction perpendicular to the first direction and connected to the first data line and the second data line;
wherein when data read out from selected memory cells of the plurality of the first memory cells is given to the first data line, the second data line and the second memory array are electrically isolated; and
wherein when data read out from selected memory cells of the plurality of the second memory cells is given to the second data line, the first data line and the first memory array are electrically isolated.
Further, the semiconductor device comprises:
a plurality of memory arrays each including a plurality of memory cells;
a plurality of first signal transmission lines provided one for each of the plurality of memory arrays and extending in a first direction; and
a second signal transmission line extending in a second direction perpendicular to the first direction and connected to the plurality of first signal transmission lines;
wherein when data read out from memory cells contained in one selected memory array of the plurality of memory arrays is supplied to the first signal transmission line that corresponds to the selected memory array, the memory arrays other than the selected memory array and the first signal transmission line corresponding to the selected memory array are electrically isolated.
Further, a semiconductor device comprises:
a first memory array including a first bit line connected with a plurality of first memory cells;
second memory array including a second bit line connected with a plurality of second memory cells;
a first signal transmission line provided for the first memory array;
a second signal transmission line provided for the second memory array;
a first switch connected between the first bit line and the first signal transmission line and controlled by a first signal;
a second switch connected between the second bit line and the second signal transmission line and controlled by a second signal;
a first circuit for receiving a third signal and a fourth signal to form the first signal; and
a second circuit for receiving the third signal and a fifth signal different from the fourth signal to form the second signal.
Further, the semiconductor device comprises:
a plurality of memory cell arrays;
a first input/output line extending in a direction parallel to a word line;
a second input/output line formed in a hierarchy different from the first input/output line and extending in a direction perpendicular to the first input/output line; and
a main amplifier and a write driver, both connected to the second input/output line;
wherein the first input/output line is formed over an area where a sense amplifier is formed;
wherein the direction perpendicular to the first input/output line is parallel to a bit line;
wherein the first input/output line and the second input/output line are connected by a conductive material filled in a through hole in an area where the sense amplifier is formed;
wherein the second input/output line is located in an area where the plurality of memory cell arrays are formed; and
wherein the second input/output line is arranged parallel to a column selection signal line.
Further a semiconductor device comprises:
a plurality of memory cell arrays;
a first input/output line extending in a direction parallel to a word line;
a second input/output line formed in a hierarchy different from the first input/output line and extending in a direction perpendicular to the first input/output line;
a third input/output line extending in a direction perpendicular to the second input/output line; and
a main amplifier and a write driver, both connected to the third input/output line;
wherein the first input/output line is formed over an area where a sense amplifier is formed;
wherein the direction perpendicular to the first input/output line is parallel to a bit line;
wherein the second input/output line is parallel to a column selection signal line;
wherein the first input/output line and the second input/output line are connected by a conductive material filled in a through hole in an area where the sense amplifier is formed;
wherein the second input/output line and the third input/output line are connected by a conductive material filled in a through hole in an area where the plurality of memory cell arrays are formed; and
wherein the second input/output line and the third input/output line are located in an area where the plurality of memory cell arrays are formed.
Further, a semiconductor device comprises:
a plurality of memory cell arrays;
a first line extending in a direction parallel to a word line;
a second line formed in a hierarchy different from the first line and extending in a direction perpendicular to the first line;
a third line extending in a direction parallel to the second line;
an interconnecting line; and
a main amplifier connected to the third line;
wherein the first line is formed over a sense amplifier area;
wherein the direction perpendicular to the first line is parallel to a bit line;
wherein the second line is parallel to a column selection signal line;
wherein the first line and the second line are connected by a conductive material filled in a through hole in a cross area for the plurality of memory cell arrays;
wherein the second line and the interconnecting line are connected by a conductive material filled in a through hole in an area where a word line driver for the plurality of the memory cell arrays is formed;
wherein the third line and the interconnecting line are connected by a conductive material filled in a through hole in an area where the plurality of the memory cell arrays are formed; and
wherein the third line is located in an area where the plurality of memory cell arrays are formed.